• DocumentCode
    1786221
  • Title

    Distributed adaptive routing for spidergon NoC

  • Author

    Bishnoi, Rajendra ; Kumar, Pranaw ; Laxmi, V. ; Gaur, M.S. ; Sikka, Apoorva

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Malaviya Nat. Inst. of Technol., Jaipur, India
  • fYear
    2014
  • fDate
    16-18 July 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Spidergon is a popular NoC (Network-On-Chip) developed to realize cost effective multi-processor SoC (MPSoC) using a fixed optimized topology [1]. Increasing diversity of applications, quality of service requirements and deterministic routing schemes inhibit the performance by creating congestion bottlenecks. This paper presents an adaptive routing algorithm that exploits the path diversity of spidergon NoC and selects the optimal path on the basis of congestion level (CL). CL depicts current traffic conditions. Proposed scheme is compared with native deterministic routing schemes of spidergon NoC i.e. aFirst and aLast. Experimental results demonstrate that our algorithm distributes traffic evenly while reducing hot-spots resulting in a considerable performance improvement.
  • Keywords
    network routing; network-on-chip; CL basis; MPSoC; Spidergon NoC; congestion level basis; deterministic routing scheme; distributed adaptive routing algorithm; fixed optimized topology; multiprocessor SoC; network-on-chip; path diversity; quality of service; Algorithm design and analysis; Clocks; Network topology; Routing; System recovery; Throughput; Topology; NoC SoC; Path diversity; adaptive;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design and Test, 18th International Symposium on
  • Conference_Location
    Coimbatore
  • Print_ISBN
    978-1-4799-5088-1
  • Type

    conf

  • DOI
    10.1109/ISVDAT.2014.6881058
  • Filename
    6881058