Design of tunnel FET based low power digital circuits

Tunnel FET (TFET) having lesser leakage current and sub-threshold slope than MOSFET which works on the principle of band-to-band tunneling is found to be a potential candidate for ultra low power electronic applications. However, it is important to analyze how these devices behave better than conventional MOSFETs in analog and digital circuits. As TFETs are now in research side, built-in models for the devices are not available in circuit simulators and thus it is not possible to simulate TFET based circuits. This work aims to include a physics-based analytical model of TFET in Cadence Design framework using Verilog-A and to design and simulate digital circuits using the integrated model. A library is created in Cadence which includes all basic logic gates based on TFET using which full adder and parity checker circuits are realized.