• DocumentCode
    1786704
  • Title

    Post-routing latch optimization for timing closure

  • Author

    Held, Stephan ; Schorr, Ulrike

  • Author_Institution
    Res. Inst. for Discrete Math., Bonn, Germany
  • fYear
    2014
  • fDate
    1-5 June 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    We present an algorithm which permutes latch positions and sizes within a clock cluster to maximize the worst slack. It preserves the clock footprint and routing, and can therefore be applied late in the design flow after clock network design.
  • Keywords
    clocks; flip-flops; microprocessor chips; network routing; optimisation; search problems; binary search; bipartite matching; clock network design; microprocessor; negative endpoint slack sum; post-routing latch optimization; timing closure; wirelength minimization; Algorithm design and analysis; Clocks; Clustering algorithms; Delays; Latches; Optimization; Clock network; latch clustering; latch planning;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1145/2593069.2593182
  • Filename
    6881334
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1786704