DocumentCode
1786778
Title
Graphical interface for simulation and analysis of LDPC block codes
Author
Medina, C. ; Zambrano, M. ; Iglesias, E.
Author_Institution
Univ. Tecnol. de Panama, Panama City, Panama
fYear
2014
fDate
12-14 Nov. 2014
Firstpage
1
Lastpage
6
Abstract
Low density parity check (LDPC) codes are one of the error-correction codes more versatile, promising and important, and have been adopted in most of the current communication standards. Given the actual and future relevance of these codes, we have developed a graphical interface for simulation and performance analysis considering several factors that affect their encoding and decoding. Thus, this interface could be useful in the design process of these codes, and also as a teaching-learning tool on this topic. In addition to the description of the interface and the analysis of simulations, importance of LDPC codes and graphical interfaces is discussed, the set of parameters and criteria considered in the simulations are described and some improvements to the current interface are suggested.
Keywords
block codes; error correction; graphical user interfaces; parity check codes; telecommunication computing; LDPC block codes; code design process; error correction codes; graphical interface; low density parity check codes; teaching-learning tool; AWGN; Algorithm design and analysis; Analytical models; Bit error rate; Decoding; Irrigation; Parity check codes; LDPC codes; LDPC codes decoding; bit-flipping algorithm; graphical interface; min-sum algorithm; sum-prod algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Central America and Panama Convention (CONCAPAN XXXIV), 2014 IEEE
Conference_Location
Panama City
Type
conf
DOI
10.1109/CONCAPAN.2014.7000430
Filename
7000430
Link To Document