Simultaneous sizing, reference voltage and clamp voltage biasing for robustness, self-calibration and testability of STTRAM arrays

Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the limited sense-margin poses challenge towards applicability of STTRAM. Reference voltage (Vref) biasing and clamp voltage (Vclamp) biasing are possible techniques to balance ‘0’ and ‘1’ sense margins for improved robustness. In this paper, we show that Vref and Vclamp biasing are more effective when employed on appropriately sized sense circuit. Our investigation also reveals that these two techniques can be used for meeting two different objectives namely, self-calibration and improved testability. We show that the proposed sizing and biasing technique can improve both robustness and testability while sacrificing minimum sense margin compared to conventional sense circuit that is designed to provide best sense margin.