DocumentCode
1786837
Title
Flushing-enabled loop pipelining for high-level synthesis
Author
Dai, Shaotao ; Mingxing Tan ; Kecheng Hao ; Zhiru Zhang
Author_Institution
Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA
fYear
2014
fDate
1-5 June 2014
Firstpage
1
Lastpage
6
Abstract
Loop pipelining is a widely-accepted technique in high-level synthesis to enable pipelined execution of successive loop iterations to achieve high performance. Existing loop pipelining methods provide inadequate support for pipeline flushing. In this paper, we study the problem of enabling flushing in pipeline synthesis and examine its implications in scheduling and binding. We propose novel techniques for synthesizing a conflict-aware flushing-enabled pipeline that is robust against potential resource collisions. Experiments with real-life benchmarks show that our methods significantly reduce the possibility of resource collisions compared to conventional approaches while conserving hardware resources and achieving near-optimal performance.
Keywords
high level synthesis; integer programming; linear programming; pipeline processing; processor scheduling; high-level synthesis; integer linear programming; loop iterations; loop pipelining; pipeline flushing; pipeline synthesis; pipelined execution; Delays; Dynamic scheduling; Pipeline processing; Pipelines; Schedules; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE
Conference_Location
San Francisco, CA
Type
conf
DOI
10.1145/2593069.2593143
Filename
6881403
Link To Document