System-level floorplan-aware analysis of integrated CPU-GPUs

Author

Nandakumar, Vivek S. ; Marek-Sadowska, Malgorzata

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, Santa Barbara, CA, USA

fYear

2014

fDate

1-5 June 2014

Firstpage

1

Lastpage

6

Abstract

Conventional, pre-RTL SoC architectural design space exploration does not account for the chip´s floorplan. However, the power and performance of integrated CPU-GPUs are highly dependent not only on architectural specifications and workload characteristics but also on the underlying floorplan. We develop a floorplan-aware system-level analysis framework for integrated CPU-GPUs and demonstrate that the overall energy efficiency can be over/under estimated by up to 25% when floorplan is not account-ed for. The floorplan-aware system-level exploration tool allows us to observe interesting dependencies between architectural choices and physical design. These observations guide the frame-work in determining energy efficient floorplans for wide-range of workloads.

Keywords

energy conservation; graphics processing units; integrated circuit layout; microprocessor chips; system-on-chip; CPU; GPU; RTL; SoC; architectural design space exploration; energy efficiency; floorplan-aware system-level analysis; Energy efficiency; Graphics processing units; Hardware; Random access memory; Sensitivity; System-on-chip; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE

Conference_Location

San Francisco, CA

Type

conf

DOI

10.1145/2593069.2593225

Filename

6881464