Title :
EC-Cache: Exploiting error locality to optimize LDPC in NAND flash-based SSDs
Author :
Ren-Shuo Liu ; Meng-Yen Chuang ; Chia-Lin Yang ; Cheng-Hsuan Li ; Kin-Chu Ho ; Hsiang-Pang Li
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Low-density parity-check (LDPC) is widely accepted as the baseline error-correction codes offering strong error-correcting capability for future NAND flash-based SSDs. However, LDPC incurs read performance overhead because of its complex decoding procedure. To mitigate such overhead, we propose the error-correcting cache (EC-Cache) that exploits the “error locality” of NAND flash. Error locality means that the majority of errors in reads to the same NAND flash page appear in the same positions until the page is erased. By caching detected errors, EC-Cache can correct a significant portion of errors present in a requested flash page before the associated LDPC decoding process begins. EC-Cache can greatly speed up LDPC decoding because LDPC´s latency is directly correlated to the number of errors present in the input data. Experimental results show that EC-Cache achieves up to 2.6× SSD read performance gain.
Keywords :
NAND circuits; cache storage; decoding; error correction codes; flash memories; parity check codes; EC-cache; LDPC decoding process; LDPC latency; NAND flash page; NAND flash-based SSD; baseline error-correction codes; decoding procedure; error locality; error-correcting cache; error-correcting capability; low-density parity-check; Bit error rate; Decoding; Encoding; Flash memories; Iterative decoding; Sensors; LDPC; NAND flash; SSD; bit errors; cache;
Conference_Titel :
Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
DOI :
10.1145/2593069.2593130