A side-channel analysis resistant reconfigurable cryptographic coprocessor supporting multiple block cipher algorithms

Author

Weiwei Shan ; Longxing Shi ; Xingyuan Fu ; Xiao Zhang ; Chaoxuan Tian ; Zhipeng Xu ; Jun Yang ; Jie Li

Author_Institution

Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China

fYear

2014

fDate

1-5 June 2014

Firstpage

1

Lastpage

6

Abstract

A side-channel analysis resistant reconfigurable cryptographic coprocessor is designed and fabricated in 0.18μm CMOS with 1.8V supply and 100MHz frequency, supporting multiple block cipher algorithms of AES, DES, RC6 and IDEA. Our countermeasure utilizes idle processing elements existed in reconfigurable array to do dummy operations to hide leakage information. This method has little impact on area and frequency, and it is flexible after silicon. It resists SPA and DPA without distinguishing the encryption region. And by correlation-based electromagnetic analysis, measurement to disclosure of DES enhances 36 times with partial countermeasures and AES discloses no subkey after more than one million electromagnetic traces with full countermeasures.

Keywords

CMOS integrated circuits; coprocessors; cryptography; CMOS; dummy operations; electromagnetic analysis; electromagnetic traces; encryption region; leakage information; multiple block cipher algorithms; side channel analysis resistant reconfigurable cryptographic coprocessor; Algorithm design and analysis; Arrays; Ciphers; Coprocessors; Encryption; Block Cipher Algorithms; Cryptographic Coprocessor; Reconfigurable architecture; Side-channel attack (SCA); correlation based differential analysis (CPA); electromagnetic analysis (EMA);

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE

Conference_Location

San Francisco, CA

Type

conf

Filename

6881503