MASH{fifo}: A hardware-based multiple cache simulator for rapid FIFO cache analysis

Cache memories have become an essential component in modern processors. To find the cache configuration that best fits the targeted power, timing and cost criteria of the system, designers conventionally run a lengthy cache simulation in software. In this paper we present MASH{fifo}, the first Multiple cAche Simulator in Hardware (MASH) supporting the FIFO replacement policy. We measured a speedup of up to 11x when compared to the fastest software alternative, CIPARSim. We also investigate an in-system implementation where multiple cache simulation is performed in real time from within an embedded system.