• DocumentCode
    1787056
  • Title

    BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation

  • Author

    Sutaria, Ketul ; Ramkumar, A. ; Rongjun Zhu ; Rajveev, Renju ; Yao Ma ; Yu Cao

  • Author_Institution
    Sch. of Electr. Comput. & Energy Eng, Arizona State Univ., Tempe, AZ, USA
  • fYear
    2014
  • fDate
    1-5 June 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    The BTI effect, which consists of both stress and recovery phases, poses a unique challenge to long-term aging prediction, because the degradation rate strongly depends on the stress pattern. Previous approaches usually resort to an average, constant stress waveform to simplify the situation. They are efficient, but fail to capture the reality, especially under dynamic voltage scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. This paper presents a suite of solutions that enable aging simulation under all possible stress conditions. Key contributions include: (1) Compact modeling of BTI when the stress voltage is varying. The results to both reaction-diffusion (RD) and trapping/detrapping (TD) mechanisms are derived. (2) Efficient simulation under DVS, leveraging the new BTI models; (3) Silicon validation at 45nm and 65nm, at both device and circuit levels. As the results illustrate, it is necessary to combine both RD and TD mechanisms to accurately predict aging under changing stress voltages. Our proposed work provides a general and comprehensive solution to aging analysis under random stress patterns.
  • Keywords
    CMOS integrated circuits; ageing; integrated circuit design; integrated circuit modelling; internal stresses; mixed analogue-digital integrated circuits; negative bias temperature instability; reaction-diffusion systems; silicon; BTI effect; BTI models; BTI-induced aging; DVS; RD mechanisms; Si; TD mechanisms; aging analysis; aging prediction; analog-mixed signal designs; bias temperature instability; compact modeling; dynamic voltage scaling; reaction-diffusion mechanisms; recovery phases; silicon validation; size 45 nm; size 65 nm; stress pattern; stress voltage; stress waveforms; trapping-detrapping mechanisms; Aging; Charge carrier processes; Data models; Integrated circuit modeling; Predictive models; Stress; Voltage control; Bias Temperature In-stability; DVS; Random Stress Waveform; Reliability Prediction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • Filename
    6881530