• DocumentCode
    1787059
  • Title

    C-Mine: Data mining of logic common cases for low power synthesis of Better-Than-Worst-Case designs

  • Author

    Chen-Hsuan Lin ; Lu Wan ; Deming Chen

  • Author_Institution
    Dept. of ECE, UIUC, Champaign, IL, USA
  • fYear
    2014
  • fDate
    1-5 June 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    The Better-Than-Worst-Case (BTW) design methodology is well-known for its potential to improve circuit energy efficiency, performance, and reliability. However, most existing methods do not provide sufficiently scalable solutions. Thus, we propose a new technique, C-Mine, which combines two scalable techniques, data mining and SAT solving, to provide scale-up solutions. Data mining can efficiently extract patterns from an enormous data set, and SAT solving is famous for its scalable verification. The experimental results show that, compared to a recent publication, C-Mine can achieve compatible performance with an additional 5% energy savings, and 50x speedup for bigger benchmarks on average.
  • Keywords
    circuit reliability; data mining; logic circuits; C-Mine; SAT solving; better-than-worst-case designs; data mining; logic common cases; low power synthesis; reliability; scalable techniques; Data mining; Data models; Delays; Indexes; Optimization; Throughput; Common case; Data Mining; Energy efficiency; Resynthesis; SAT solving; Scalability; Timing error resilience;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1145/2593069.2593107
  • Filename
    6881532