Title :
A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy
Author :
Wen-Hao Liu ; Zhen-Yu Peng ; Ting-Chi Wang
Author_Institution :
Cadence Design Syst., ICD, Austin, TX, USA
Abstract :
Routability has become a challenging issue with designs scaling down. Recently, global-routing-based routing congestion estimators (GRCEs) are widely used to detect the routability problems in the early VLSI design stages. To make GRCEs fast, using parallel routing approaches to speed up GRCEs is a promising direction. However, integrating existing parallel routing approaches into a GRCE may degrade the accuracy of the GRCE, because the routing kernel of the GRCE has to be modified such that its routing behavior changes. This paper presents a resource-level parallel approach (RPA) to accelerate GRCEs. RPA is easy to implement and has no need to change the routing kernels of GRCEs. Thus, GRCEs accelerated by RPA can keep its routing behavior and the estimation accuracy. Moreover, this paper presents an analytical method to quantify the estimation accuracy of a GRCE. Traditionally, the accuracy of a GRCE is manually measured by how they look like between the congestion maps generated by the GRCE and a real router, which may be inaccurate and time-consuming. In contrast, using the proposed quantifying method to evaluate the accuracy of a GRCE is more precise and faster.
Keywords :
VLSI; estimation theory; integrated circuit interconnections; network routing; GRCE; RPA; VLSI design; estimation accuracy; global-routing-based routing congestion estimation; parallel routing; resource-level parallel approach; routing kernel; Acceleration; Accuracy; Dispatching; Estimation; Measurement; Nickel; Routing;
Conference_Titel :
Computer-Aided Design (ICCAD), 2014 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
DOI :
10.1109/ICCAD.2014.7001381