Title :
Constrained interpolation for guided logic synthesis
Author :
Petkovska, Ana ; Novo, David ; Mishchenko, Alexander ; Ienne, Paolo
Author_Institution :
Sch. of Comput. & Commun. Sci., Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
Abstract :
Craig interpolation is a known method for expressing a target function f as a function of a given set of base functions G. The resulting interpolant represents the dependency function h, such that f = h(G). Generally, the set G contains enough base functions to enable the existence of multiple dependency functions whose quality mainly depends on which base functions were selected for reconstruction. The interpolation is not an optimisation problem and thus, often, it selects some random base functions and, particularly, omits others potentially required for an optimal implementation of the target function. Mainly, it is impossible to impose that the interpolant uses a specific base function. In this paper, we propose a method that forces a specific base function gi as a primary input of a dependency function. Such a dependency function is built as a Shannon expansion of two constrained Craig interpolants for the assignments of the primary inputs for which gi evaluates to 0 and 1, respectively. We also introduce a method that iteratively imposes a predefined set of base functions. In each iteration, we generate a new dependency function for use as the target function of the next iteration in order to force the use of a base function. We show that, unlike the standard Craig interpolation method, our carving method succeeds to impose the desired base functions with very high probability. It recomposes single-output logic circuits as their delay- or area-optimised implementations regardless of the input implementation. The proposed methods can be efficiently employed for rewriting circuits in some synthesis-based algorithms.
Keywords :
interpolation; logic circuits; logic design; probability; random processes; Craig interpolation; Shannon expansion; area-optimised implementation; carving method; constrained interpolation; delay-optimised implementation; guided logic synthesis; interpolant; multiple dependency function; probability; random base function; rewriting circuit; single-output logic circuit; synthesis-based algorithm; target function; Boolean functions; Interpolation; Logic circuits; Logic gates; Optimization; Standards; Vectors;
Conference_Titel :
Computer-Aided Design (ICCAD), 2014 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
DOI :
10.1109/ICCAD.2014.7001392