Logic synthesis and a generalized notation for memristor-realized material implication gates

The paper presents new logic synthesis methods for single-output incomplete multi-level binary circuits using Memristor-based material implication gates. The first method follows Lehtonen´s assumption of using only two working memristors. The algorithm minimizes the number of implication (IMPLY) gates, which corresponds to minimizing the number of pulses or the delay time. This greedy search method uses essential and secondary essential primes, does not require solving the covering problem, is fast, and produces high quality results. We compare it to other synthesis methods, such as the modified SOP and Exclusive-Or Sum of Products (ESOP) with minimum number of working memristors. We analyze the problem of reduction in IMPLY gate count by adding more working memristors and introduce Imply Sequence Diagrams, a new notation, similar to one used in reversible logic.