Evolving physical design paradigms in the transition from 20/14 to 10nm process technology nodes

Advanced IC process technology nodes (28,20,14nm and below) have relied on the synergy of process-aware physical design and physical verification methodologies with design-aware yield engineering (on the manufacturing side), in order to fulfill ITRS scaling and performance requirements. These capabilities include not only additional design rules, or additional modeling capabilities, or incremental verification tools, but rather a qualitatively new set of DFM/DEM (Design For Manufacturing - Design Enabled Manufacturing) methodologies aimed at variability management, i.e. at characterization and remapping of systematic variability effects caused by design/process interaction. A typical example is a “correct by construction” router flow, augmented with yield detractor and yield enhancer patterns, implemented for 20nm high performance processor designs. In such a flow, timing (on the design side) and yield (on the manufacturing side) are co-optimized, in order to guarantee high yield and specified parametric performance in the first silicon run. In spite of current successes the incremental path down to 14nm will be disrupted, because of the hard physical limits simultaneously occurring in geometric scaling and electrical scaling, and the transition to 10 and 7 nm nodes will require a (re)volutionary DFM (Design For Manufacturing) paradigm. Building on the state-of-the-art in design/technology co-optimization this work will review the three most likely design/process scenarios for 10 and 7nm design enablement, which could potentially allow the synthesis of the “design gap” and “patterning gap” altogether.