Random walk based capacitance extraction for 3D ICs with cylindrical inter-tier-vias

Three-dimensional integrated circuits (3D ICs) make use of the vertical dimension for smaller footprint, higher speed, lower power consumption, and better timing performance. In 3D ICs, the inter-tier-via (ITV) is a critical enabling technique because it forms vertical signal and power paths. Accordingly, it is imperative to accurately and efficiently extract the electrostatic capacitances of ITVs using field solvers. Unfortunately, the cylindrical via shape presents major challenges to most of the existing methods. To address this issue, we develop a novel floating random walk (FRW) method by rotating the transition cube to suit the cylindrical surface and devising a special space management technique. Experiments on typical ITV structures suggest that the proposed techniques can accelerate the existing FRW and boundary element method (BEM) based algorithms by up to 20X and 180X, respectively, without loss of accuracy. In addition, compared with the naïve square approximation approach, our techniques can reduce the error by 10X. Large and multi-dielectric structures have been tested to demonstrate the versatility of the proposed techniques.