DocumentCode :
1788634
Title :
Proposal for parallel fixed point implementation of a radial basis function network in an FPGA
Author :
de Souza, Alisson C. D. ; Fernandes, Marcelo A. C.
Author_Institution :
Dept. of Comput. Eng. & Autom. - DCA, Fed. Univ. of Rio Grande do Norte - UFRN Natal - RN, Natal, Brazil
fYear :
2014
fDate :
5-7 Nov. 2014
Firstpage :
1
Lastpage :
6
Abstract :
This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate, and interpolation using the sine function, were also analyzed in hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.
Keywords :
field programmable gate arrays; interpolation; least mean squares methods; logic gates; radial basis function networks; ANN response; FPGA; LMS algorithm; RBF; Virtex-6 xc6vcx240t-1ff1156; XOR gate; Xilinx; artificial neural network; field programmable gate array; hardware implementation; interpolation; least mean square algorithm; nonlinear classification; parallel fixed point implementation; processing time; radial basis function network; sine function; system generator platform; Delays; Equations; Field programmable gate arrays; Mathematical model; Neurons; Table lookup; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Programmable Logic (SPL), 2014 IX Southern Conference on
Conference_Location :
Buenos Aires
Print_ISBN :
978-1-4799-6846-6
Type :
conf
DOI :
10.1109/SPL.2014.7002204
Filename :
7002204
Link To Document :
بازگشت