Title :
Hardware design of an NTT-based polynomial multiplier
Author :
Renteria-Mejia, C.P. ; Velasco-Medina, J.
Author_Institution :
Bionanoelectronics Res. Group, Univ. del Valle, Cali, Colombia
Abstract :
This paper presents the design of a parameterizable n-coefficient polynomial multiplier based on an n-point NTT-core, which uses a systolic array. The designed NTT-based polynomial multiplier is described in generic structural VHDL; synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13; verified using Modelsim; and performs the product of two polynomials of degree 4095 in 95.64 μs. The hardware synthesis and performance results show that the designed polynomial multiplier presents a good area-time trade-off and it is suitable for hardware implementations of lattice-based cryptosystems.
Keywords :
hardware description languages; number theory; polynomials; systolic arrays; NTT-based polynomial multiplier; area-time trade-off; generic structural VHDL; hardware design synthesis; lattice-based cryptosystems; modelsim; n-point NTT-core; number theoretical transform; parameterizable n-coefficient polynomial multiplier; quartus II V.13; stratix EP4SGX230KF40C2; systolic array; Algorithm design and analysis; Arrays; Clocks; Convolution; Cryptography; Hardware; Polynomials; NTT; hardware architectures for cryptography; lattice-based cryptography; polynomial multiplier; post-quantum cryptography; secure computing;
Conference_Titel :
Programmable Logic (SPL), 2014 IX Southern Conference on
Conference_Location :
Buenos Aires
Print_ISBN :
978-1-4799-6846-6
DOI :
10.1109/SPL.2014.7002209
