Design and implementation of decimal fixed-point square root in LUT-6 FPGAs

This paper presents the design and implementation of a digit-recurrence algorithm for determining the decimal square root in a 6-input LUT-based FPGA device. The design is based on the efficient use of resources such as the carry-chain originally devoted to the binary addition. Clock frequencies of 98.5 MHz (71 ns latency), 93.4 Mhz (173 ns latency) and 84.7 MHz (402 ns latency) were obtained for operand widths of 7, 16 and 34 digits, respectively, in a Xilinx Virtex 6 FPGA.