Title :
Design and implementation of decimal fixed-point square root in LUT-6 FPGAs
Author :
Vazquez, Manuel ; Tosini, Marcelo
Author_Institution :
Inst. de Investig. en Comput. Aplic. (Intia), Univ. Nac. del Centro de la Prov. De Buenos Aires (UNCPBA), Tandil, Argentina
Abstract :
This paper presents the design and implementation of a digit-recurrence algorithm for determining the decimal square root in a 6-input LUT-based FPGA device. The design is based on the efficient use of resources such as the carry-chain originally devoted to the binary addition. Clock frequencies of 98.5 MHz (71 ns latency), 93.4 Mhz (173 ns latency) and 84.7 MHz (402 ns latency) were obtained for operand widths of 7, 16 and 34 digits, respectively, in a Xilinx Virtex 6 FPGA.
Keywords :
field programmable gate arrays; 6-input device; LUT-6 FPGA; Xilinx Virtex 6; binary addition; carry-chain; decimal fixed-point square root; digit-recurrence algorithm; frequency 84.7 MHz; frequency 93.4 MHz; frequency 98.5 MHz; Decision support systems; Decimal arithmetic; FPGA; Square root;
Conference_Titel :
Programmable Logic (SPL), 2014 IX Southern Conference on
Conference_Location :
Buenos Aires
Print_ISBN :
978-1-4799-6846-6
DOI :
10.1109/SPL.2014.7002211
