Burst-mode asynchronous controller implementation on FPG using relative timing

A new methodology for the design of glitch free burst-mode asynchronous controllers on FPGAs is presented. The approach is based on relative timing, which enables timing driven asynchronous design. On ASICs, relative timing based asynchronous designs have achieved notable benefits in terms of power, performance and area, when compared to their synchronous counterparts. This paper adopts the relative timing based design methodology on FPGAs and presents a methodology to extract and map timing constraints to guarantee correct operation. The method presented in this paper can be used to implement a wide variety of burst-mode controllers, across various FPGAs. This will form the foundation for seamless ASIC prototyping of asynchronous designs on FPGAs as well as implementation of low power asynchronous designs on FPGAs.