Title :
miniFPGA: An educational app for teaching partitioning, placemnent and routing on Andriod devices
Author :
Moreno-Villalon, Adrian ; Guerra-Martin, Angel ; Boemo, Eduardo
Author_Institution :
DSLab, Univ. Autonoma de Madrid, Cantoblanco, Spain
Abstract :
In this paper is presented an educational application for teaching ideas related to partitioning, placement and routing (PPR) of digital circuit in a generic FPGA (Field-Programmable Gate Arrays) architecture. Tapping in the tactile screen, the student can construct different blocks. They can fill the contents of LUTs (Look-up Tables) and wire them activating segments of a programmable interconnection network. The program works on Android telephones and tablets. The application includes a tutorial, a set of exercises, and auxiliary tools for checking the results or sends them by e-mail.
Keywords :
computer aided instruction; computer science education; digital circuits; electronic mail; field programmable gate arrays; haptic interfaces; logic partitioning; mobile learning; network routing; smart phones; table lookup; teaching; Android devices; LUT; PPR; digital circuit; e-mail; educational application; generic FPGA architecture; generic field-programmable gate array architecture; look-up tables; miniFPGA; partitioning; placement; programmable interconnection network; routing; tactile screen; teaching; Education; Field programmable gate arrays; IEEE Press; Integrated circuit interconnections; Routing; Smart phones; Table lookup; Android; Digital Design; FPGA; Look-up Tables; Shannon Co-factoring; Technology Mapping;
Conference_Titel :
Programmable Logic (SPL), 2014 IX Southern Conference on
Conference_Location :
Buenos Aires
Print_ISBN :
978-1-4799-6846-6
DOI :
10.1109/SPL.2014.7002217
