FPGA implementation of a FEC decoding subsystem for a DVB-S2 receiver

This paper presents the implementation of a FEC decoding subsystem for a DVB-S2 compliant receiver. The FEC decoder is composed by three blocks: De-interleaver, LDPC and BCH decoders, and its main goal is correcting the bits that were corrupted by the channel during transmission. The DVB-S2 standard defines several coding schemes and interleaving methods for protecting the data, and all the configurations were considered in this implementation. This work presents the structure and functionality of the FEC subsystem, the platform that was assembled for measuring its performance, and the FPGA synthesis and BER performance results.