FPGA implementation of a FEC decoding subsystem for a DVB-S2 receiver

Author

Alves, Denise C. ; Chaves, Cesar G. ; de Lima, Eduardo R. ; da Silva, Gabriel S. ; Queiroz, Augusto F. R.

Author_Institution

Eldorado Res. Inst., Campinas, Brazil

fYear

2014

fDate

5-7 Nov. 2014

Firstpage

1

Lastpage

6

Abstract

This paper presents the implementation of a FEC decoding subsystem for a DVB-S2 compliant receiver. The FEC decoder is composed by three blocks: De-interleaver, LDPC and BCH decoders, and its main goal is correcting the bits that were corrupted by the channel during transmission. The DVB-S2 standard defines several coding schemes and interleaving methods for protecting the data, and all the configurations were considered in this implementation. This work presents the structure and functionality of the FEC subsystem, the platform that was assembled for measuring its performance, and the FPGA synthesis and BER performance results.

Keywords

data protection; decoding; digital video broadcasting; field programmable gate arrays; forward error correction; parity check codes; BCH decoders; BER performance; Bose-Chaudhuri-Hocquenghem decoder; DVB-S2 compliant receiver; FEC decoding subsystem; FPGA synthesis; LDPC decoders; data protection; de-interleaver decoders; digital video broadcasting system for satellite broadcasting and unicasting; forward error correction subsystem; low density parity check code; Bit error rate; Decoding; Digital video broadcasting; Forward error correction; Parity check codes; Signal to noise ratio; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic (SPL), 2014 IX Southern Conference on

Conference_Location

Buenos Aires

Print_ISBN

978-1-4799-6846-6

Type

conf

DOI

10.1109/SPL.2014.7002218

Filename

7002218