Title :
A novel architecture for CIC decimation filter
Author :
Sachin, B.R. ; Ullas, B.S.
Author_Institution :
Dept. of Electron. & Commun., R.V. Coll. of Eng., Bangalore, India
Abstract :
Cascaded Integrator Comb (CIC) structure is used extensively in the design of a decimation filter. This paper analyses the existing design of decimation filter and proposes a new design with reduced hardware requirements. The designs are modelled using VHDL, simulated using ISim and implemented in Spartan 3E FPGA. The synthesis report shows the reduction in number of I/O bits.
Keywords :
digital filters; field programmable gate arrays; hardware description languages; integrated circuit design; CIC decimation filter; I-O bits; ISim; Spartan 3E FPGA; VHDL; cascaded integrator comb structure; hardware requirement reduction; Clocks; Digital filters; Field programmable gate arrays; Hardware; Registers; Speech; Switches; CIC filter structure; Decimation; FPGA; ModelSim;
Conference_Titel :
Advances in Electronics, Computers and Communications (ICAECC), 2014 International Conference on
Conference_Location :
Bangalore
DOI :
10.1109/ICAECC.2014.7002388
