A low phase noise 10-G bits/s clock and data recovery circuit with modified D latch for backplane applications using dual loop architecture

Author

Sharma, D. Pavan Kumar ; Rao, Patri Sreehari ; Krishna Prasad, K.S.R.

Author_Institution

Nat. Insitute of Technol., Warangal, India

fYear

2014

fDate

10-11 Oct. 2014

Firstpage

1

Lastpage

6

Abstract

In this paper a clock and data recovery circuit (CDR) with modified D latch is designed meeting the standards of 10 Base-KR standard backplane. The designed circuit employs dual loop architecture in 0.18μm UMC CMOS technology. The simulated results indicate a phase noise of voltage controlled oscillator (VCO) as -173.782dBC/HZ, VCO gain of 350MHz/V while consuming 85mW from 1.8V supply. LC oscillator is designed for achieving low jitter.

Keywords

CMOS logic circuits; LC circuits; clock and data recovery circuits; flip-flops; phase noise; voltage-controlled oscillators; 10 Base-KR standard backplane; CDR; D latch; LC oscillator; UMC CMOS technology; VCO; backplane applications; clock and data recovery circuit; dual loop architecture; low phase noise; power 85 mW; size 0.18 mum; voltage 1.8 V; voltage controlled oscillator; Backplanes; Clocks; Detectors; Impedance; Phase noise; Tracking loops; Voltage-controlled oscillators; Phase locked loop; V-I converter; clock and data recovery circuit; current mode logic; phase detectors; phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Electronics, Computers and Communications (ICAECC), 2014 International Conference on

Conference_Location

Bangalore

Type

conf

DOI

10.1109/ICAECC.2014.7002417

Filename

7002417