Nanosecond delay level shifter with logic level correction

The power consumption is a major concern for emerging applications like mobile phones, digital cameras, pace makers and multimedia processors. The power consumption can decreases by number of ways. The multiple supply voltage design is a dominant technique for the reduction of power consumption in System on Chips/Cores. The System on Chips /Cores uses level shifters and the level shifter will become overhead, when its own power consumption & delay is high. In this paper a nanosecond delay level Shifter with logic level correction circuit is introduced that performs level up shifting as well as logic level correction to keep the VOUT stable, equals to VDD or VSS with low power consumption. The circuit is designed and simulated in a 90nm process technology. The proposed technique is a unique component, will comprise a feedback network to keep the output as stable as possible. Robustness of the new level shifter design has examined at an operating frequencies of 10 KHz, 500 KHz, & 1 MHz with varying load of 10 fF to 70 fF and varying temperature from - 20 °C to 70 °C. The proposed design reliably shifts 0.4V input signal to 1V output signal with a delay as low as 0.8ns and average power consumption of 80nW at a frequency of 1MHz.