High performance using synchronous elastic circuits with lower overheads

To get reduced area and power overheads in Synchronous elasticity implementation circuits. We are using combinations of various elasticity approaches with specific implementation technique. Elasticity refers a circuit in which circuits can tolerate arbitrary latency and delay variations in their computation units as well as communication channels. This paper gives different optimization approaches with controlled implementation to reduce these area and power overheads of elastic control network without sacrificing the control network performance. Ultra simple fork (USFork), early evaluation join (EEJoin), half-buffer retiming (HBR) controller, eager Fork, join, lazy fork combinations for implementation are introduced. In this approach we checked all node and all combinational blocks clock period and uses elastic buffer only when it needed. Comparing to published work on a miniMIPS processor case study and Synchronous elasticization at reduced cost, our implementation shows up to 8% and 15.08% area and power overheads due to proposed flow of implementing Synchronous elasticization and up to 25 % increase in throughput i.e. 1 G bits/sec.