VLSI implementation of discrete cosine transform and Intra prediction

This paper presents VLSI implementation of DCT algorithms for HEVC application. Here transform units (TU) of sizes 4×4 to 16×16 are implemented in both conventional method and partial butterfly model using multiplier-less multiple constant methods to reduce the hardware cost. Both the methods are designed using Verilog HDL, verified and compared for the realisation of hardware cost. We found that power and hardware utilization may be reduced by using MCM technique than conventional method. Along with DCT, Intra prediction algorithm is implemented. In the previous standards H.264, only 9 Intra prediction modes were used for the block size of 4×4 to 16×16. In the HEVC application the block sizes are increased from 4×4 to 64×64 and even the modes are increased to 34, to provide high performance gain. This is implemented using Verilog HDL. The functional verification, comparison and simulation are done using ISim simulator provided by Xilinx software. The synthesis results are obtained using RTL compiler provided by cadence software.