Design of speed and power efficient multipliers using vedic mathematics with VLSI implementation

Multipliers are the key components of systems viz. FIR filters, Microprocessors, Digital Signal Processors etc. which demands high performance. The performance of these applications mainly depends on the numbers of multiplication done in unit time. In real time multipliers the speed and power are the major criteria, thus faster and power efficient multipliers are needed. This paper focuses on the development of high speed, low power multipliers using Vedic Mathematics. The proposed multiplier architectures are based on the Urdhva and Nikhilam sutras of the Vedic Mathematics. The Urdhva multiplier generates the partial products and the sums in parallel. Hence, this multiplier reduces the carry propagation delay from LSB to MSB. The Nikhilam multiplier finds the compliment of the larger number of its nearest base, thus reduces the complexity in the multiplication. The proposed multipliers are designed using Carry save adder and implemented in 65nm CMOS Technology using ASIC methodology. The proposed Urdhva and Nikhilam multipliers achieve 60%, 77% improvement in speed and 37%, 50% improvement in power respectively, as compared with the power consumption of the conventional array multipliers.