Title :
Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem
Author :
Tsung-Chuan Ma ; Tung-Chien Chen ; Liang-Gee Chen
Author_Institution :
Grad. Inst. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
It is impractical to apply a general spike sorting algorithm for every subject because of the individual characteristics of brain signal. Furthermore, extracting more neural activities for higher accuracy of spike sorting requires more input electrodes as well as large power consumption and chip area. Therefore, several practical constraints are considered in this work when implementing a programmable spike sorting hardware with large number of input channels. In this paper, we provide a 128-channel spike detection processor for spike sorting microsystem without compromise of the power efficiency. This chip consumes only 87.02uW and 9.7uW/mm2 of power density, fabricated with 90nm low-leakage CMOS process.
Keywords :
CMOS integrated circuits; VLSI; integrated circuit design; low-power electronics; microprocessor chips; neural chips; 128-channel spike sorting microsystem; VLSI architecture design; brain signal characteristics; chip area; general spike sorting algorithm; input electrodes; low power spike detection processor design; low-leakage CMOS process; neural activity; power consumption; power density; power efficiency; programmable spike sorting hardware; size 90 nm; Density measurement; Detection algorithms; Neurons; Power demand; Power system measurements; Random access memory; Sorting; Neural Signal Processing; Spike Detection; Spike Sorting;
Conference_Titel :
Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on
Conference_Location :
Florence
DOI :
10.1109/ICASSP.2014.6854330
