Reusable DCT architecture for parallel processing of Y, U and V transforms in HEVC

In 2D Discrete Cosine Transform (DCT) hardware, most of the transpose memory remains unutilized when the size of input is smaller than the maximum supported size. This paper proposes a scheme for the DCT module in the HEVC encoder to exploit this unused memory and thus, to increase throughput through parallel processing. In the proposed architecture, transforms of Y, U and V residual blocks for TUs (Transform Units) smaller than 32×32 can be calculated in parallel. Experimental results show that a significant number of cycles are saved when compared to a conventional serial DCT hardware at a marginal increase in hardware cost.