Title :
Multi-level virtual model of Aldebaran AP SoC
Author :
Jae-Jin Lee ; Kyungjin Byun ; Nakwoong Eum
Author_Institution :
Multimedia Processor Res., ETRI, Daejeon, South Korea
Abstract :
There are ongoing efforts to enable development and optimization of hardware and software simultaneously. It is believed that the most effective solution is a system-level virtualization based on a virtual model. This paper proposes a multi-level virtual model of our 32-bit RISC Aldebaran AP with support for several features that further enhances system development efficiency.
Keywords :
reduced instruction set computing; system-on-chip; virtualisation; RISC Aldebaran AP SoC; dynamic binary translation; multilevel virtual model; system-level virtualization; system-on-chip; word length 32 bit; Decoding; Emulation; Field programmable gate arrays; Hardware; Multicore processing; Software; System-on-chip; Aldebaran; DBT; Virtual Model;
Conference_Titel :
Consumer Electronics (ISCE 2014), The 18th IEEE International Symposium on
Conference_Location :
JeJu Island
DOI :
10.1109/ISCE.2014.6884306
