STT-RAM reliability enhancement through ECC and access scheme optimization

Author

Wujie Wen ; Yaojun Zhang ; Mengjie Mao ; Yiran Chen

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA

fYear

2014

fDate

22-25 June 2014

Firstpage

1

Lastpage

2

Abstract

Multi-level cell Spin-Transfer Torque RAM (MLC STT-RAM) greatly suffers from the significantly degraded operation reliability and high programming cost. In this paper, a novel MLC design, namely ternary-state MLC (TS-MLC STT-RAM), is proposed for high-reliable high-performance memory systems by leveraging a cross-layer solution set. Based on the structure, several circuit and architecture schemes are proposed to enhance both the reliability and access latency of the memory cells.

Keywords

error correction codes; integrated circuit design; integrated circuit reliability; random-access storage; ECC; MLC design; STT-RAM reliability enhancement; TS-MLC STT-RAM; access latency; access scheme optimization; cross-layer solution set; high-reliable high-performance memory systems; memory cells; multilevel cell spin-transfer torque RAM; operation reliability; programming cost; ternary-state MLC; Computer architecture; Error analysis; Microprocessors; Programming; Random access memory; Reliability; Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics (ISCE 2014), The 18th IEEE International Symposium on

Conference_Location

JeJu Island

Type

conf

DOI

10.1109/ISCE.2014.6884324

Filename

6884324