Maximizing DRAM performance using selective operating frequency boosting

Advance of semiconductor manufacturing technology enables nano-scale processes for chip fabrication. However, process variation gets worse as the scales down, and finally causes performance discrepancies among the dies in a wafer and the transistors in a die. Especially in conventional Dynamic Random Access Memory (DRAM), billions of memory cells are contained in the devices and each cell is composed of one transistor and one capacitor. Therefore, at a fine-grain level, operating frequency of the DRAM device is determined by the memory cell which has the lowest performance. The fact implies that some region of the device can operate with a higher frequency than a manufacturer marked. In this paper, we propose a selective operating frequency boosting scheme of DRAM device to provide improved performance. We show the feasibility of the proposed scheme according to the portion of the boosting enabled portion.