DocumentCode :
1790428
Title :
Memory optimization of bilateral filter and its hardware implementation
Author :
Jung-Min Choi ; Sung-Joon Jang ; Sang-Seol Lee ; Youngbae Hwang ; Byeong Ho Choi
Author_Institution :
Multimedia IP Res. Center, Korea Electron. Technol. Inst., Seongnam, South Korea
fYear :
2014
fDate :
22-25 June 2014
Firstpage :
1
Lastpage :
2
Abstract :
As a method for edge-preserving or noise-reducing, a bilateral filter is widely used. However, because every pixel in a filtering window needs a separate Look-Up Table (LUT) for the parallel processing, its hardware implementation is still bulky. In this paper, we propose Similar Weight Grouping (SWG) which maps multiple indexes with a similar value onto a single index and Zero Value Suppression (ZVS) which removes indexes with a value of almost zero to reduce a size of the LUT. By our scheme, a total size of LUT is reduced by approximately 95% while maintaining its performance. Finally, it is implemented using 7.7 KB on-chip memory and 93.1 Kgates with 65 nm process.
Keywords :
group theory; image denoising; nonlinear filters; optimisation; parallel processing; table lookup; 93.1 Kgates; KB on-chip memory; LUT; SWG; ZVS; bilateral filter; edge-preservation; filtering window; hardware implementation; look-up table; memory optimization; multiple index map; noise-reduction; parallel processing; similar weight grouping; single index; size 65 nm; zero value suppression; Filtering; Hardware; IP networks; Indexes; System-on-chip; Table lookup; Zero voltage switching; bilateral filter; look-up table; similar weight grouping; zero value suppression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics (ISCE 2014), The 18th IEEE International Symposium on
Conference_Location :
JeJu Island
Type :
conf
DOI :
10.1109/ISCE.2014.6884437
Filename :
6884437
Link To Document :
بازگشت