Design of a multi-rate quasi-cyclic low-density parity-check encoder based on pipelined rotate-left-accumulator circuits

Author

Fei Wang ; Peng Zhang ; Xin Wan ; Jin Liu

Author_Institution

Sch. of Inf. Eng., Commun. Univ. of China, Beijing, China

fYear

2014

fDate

14-16 Oct. 2014

Firstpage

1105

Lastpage

1109

Abstract

A serial-input serial-output encoder based on pipelined rotate-left-accumulator (RLA) circuits is designed for multi-rate Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of Chinese digital terrestrial/television multimedia broadcasting (DTMB) standard. The RLA circuit can make the area usage economical, and the pipelined architecture can simplify the memory structure. The encoder is implemented on FPGA. Simulation results demonstrate that the design meets the requirement of DTMB standard with lower energy consumption and fewer hardware resources.

Keywords

cyclic codes; digital television; field programmable gate arrays; parity check codes; television broadcasting; Chinese digital television multimedia broadcasting standard; Chinese digital terrestrial multimedia broadcasting standard; DTMB standard; FPGA; QC-LDPC code; hardware resource; lower energy consumption; multirate quasicyclic low density parity check encoder design; pipelined RLA circuit; pipelined rotate-left-accumulator circuit; serial-input serial-output encoder; Clocks; Generators; Logic gates; Parity check codes; Registers; Standards; Table lookup; DTMB; Encoder; FPGA; QC-LDPC; Rotate-Left-Accumulator(RLA);

fLanguage

English

Publisher

ieee

Conference_Titel

Image and Signal Processing (CISP), 2014 7th International Congress on

Conference_Location

Dalian

Type

conf

DOI

10.1109/CISP.2014.7003945

Filename

7003945