Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs

Validation of an embedded test technique in terms of its expected yield loss and test escape metrics is a key step before it can be deployed in high-volume manufacturing. However, performing this validation at the design stage usually demands extensive computational resources, which may render electrical simulations infeasible. In this paper, we propose a digital test technique for dynamic test of ΣΔ ADCs based on a digital ternary stimulus together with an advanced simulation framework for its validation. The proposed simulation strategy relies on a combination of transistor-level simulations, behavioural simulations, and statistical tools. To show the feasibility of our approach, we use the proposed validation framework to compare the ternary stimulus with a digital bitstream stimulus, as well as with a standard high-resolution analog sine-wave stimulus.