DocumentCode
1791481
Title
A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms
Author
Cucchetto, Filippo ; Lonardi, Alessandro ; Pravadelli, Graziano
Author_Institution
Dept. of Comput. Sci., Univ. of Verona, Verona, Italy
fYear
2014
fDate
6-8 Oct. 2014
Firstpage
1
Lastpage
6
Abstract
Several approaches have been proposed for cosimulation between QEMU and SystemC. On the contrary, no paper addresses integration between Open Virtual Platform (OVP) and SystemC. Indeed, OVP models and the related simulator can be integrated into SystemC designs by using TLM 2.0 wrappers and opportune OVP APIs. However, this solution presents some disadvantages, like the incapability of supporting cycle-accurate models, and the necessity of re-design, in terms of SystemC modules, all OVP components that should be integrated in the target platform. To avoid such drawbacks, and provide an easy way to port SystemC models from a QEMU-based to an OVP-based virtual platform and vice versa, this paper presents a common co-simulation approach that works for integrating SystemC components with both QEMU and OVP.
Keywords
application program interfaces; virtual prototyping; OVP virtual platforms; QEMU platforms; SystemC designs; TLM 2.0 wrappers; common cosimulation approach; cycle-accurate models; open virtual platform; opportune API; virtual prototyping; Bridges; Computer architecture; Hardware; Operating systems; Time-varying systems; Virtual prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on
Conference_Location
Playa del Carmen
Type
conf
DOI
10.1109/VLSI-SoC.2014.7004154
Filename
7004154
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