Optimized active and power-down mode refresh control in 3D-DRAMs

3D stacked systems with Wide-I/O DRAMs are the future density optimized mobile computing platforms. Unfortunately, with 3D integration, the power densities and thermal dissipation are increased dramatically. In this paper, we investigate the effectiveness of power-down mode policies (using precharge power down, active power-down and self-refresh) and bank-wise refresh in active mode. We run real-life benchmarks to quantify the impact of each power-down mode setting. We derive a power-down mode policy which shows up to 10% energy reduction in high activity periods and up to 13% in idle phases. Further, we improve DRAM refresh power by considering the lateral and vertical temperature variations in the 3D structure and adapting the per-DRAM-bank refresh period accordingly. To achieve this, a per DRAM array hotspot detector, designed with DRAM cells and circuits, is used to acquire temperature and refresh information directly from the DRAM array. We show 16% improvements in DRAM refresh power due to hotspot detectors inside the DRAM enabling temperature variation aware bank-wise refresh. For all the above mentioned investigations a detailed DRAM controller model with accurate functionality, timing, and power estimation in SystemC TLM-2.0 (Transaction Level Modeling) and a highly sophisticated virtual hardware platform are mandatory to achieve a through analysis.