Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors

This paper addresses the reordering of coefficients, i.e., twiddle factors in multicore FFT in order to obtain power efficient datapaths. The coefficients are divided in smaller ones into the different cores and they are reordered through the Improved Anedma heuristic-based algorithm. According to the characteristics of the FFT algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering of these operations, into each core, can contribute for the reduction of the switching activity, what leads to the minimization of power consumption in the FFTs. Therefore, the appropriate ordering of coefficients in the different cores allows finding the best architecture in terms of both performance and power consumption. The FFT architectures were synthesized using SYNOPSYS Design Compiler for the XFAB 180 nm technology. The results show that it is possible to achieve power reduction in the FFTs close to 9%, on average, after reordering the twiddle factors in the different cores.