Title :
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study
Author :
Miorandi, Gabriele ; Ghiribaldi, Alberto ; Nowick, Steven M. ; Bertozzi, Davide
Author_Institution :
Univ. of Ferrara Ferrara, Ferrara, Italy
Abstract :
In on-chip interconnection networks, performance optimization techniques can be often achieved in two opposite ways: by making control logic more complex inside switches, or by pushing design complexity to the switch boundaries. The implementation of virtual channel (VC) flow control is an important application domain of this design trade-off. The data path of VC switches typically exhibits replicated buffers. The underlying philosophy (i.e., resource replication) can be pushed to the limit, thus incuring an apparently high area cost, while simplifying the switch control path. On the other hand, unreplicated resources require complex control logic for the sake of their efficient sharing among virtual networks. Investigating this design tradeoff is especially important for asynchronous networks, where the synthesis of complex control circuits is a challenge. This paper is a first step toward a design space exploration of VC implementation techniques for transition-signalling bundled-data asynchronous NoCs, and contrasts a VC switch with replicated crossbars against a unified-crossbar architecture relying on multistage switch allocation.
Keywords :
asynchronous circuits; network-on-chip; VC flow control; asynchronous NoC; asynchronous networks; complex control circuits; control logic; crossbar replication; design complexity; design space exploration; multistage switch allocation; on-chip interconnection networks; performance optimization techniques; resource replication; transition-signalling bundled-data; virtual channel flow control; Ports (Computers); Protocols; Resource management; Routing; Sensors; Switches;
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on
Conference_Location :
Playa del Carmen
DOI :
10.1109/VLSI-SoC.2014.7004164