Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification

This paper presents design rule checking (DRC) methods to address challenges caused by non-Manhattan geometries that are widely present in photonic integrated circuit (PIC) physical designs. Verifying such layouts with traditional DRC tools results in a huge number of false errors that are impossible to debug; and some physical rules are simply uncheckable. We demonstrate the use of an extended DRC technique on photonic designs to tackle these issues. The results show that the technique is well-suited for silicon photonics DRC, enabling false errors to be filtered in a controllable manner, leading to easier debugging with layout annotation; multi-dimensional rule checking to be performed; and mathematical expressions to be used for more accurate descriptions of physical rules.