Energy-efficient partitioning of hybrid caches in multi-core architecture

This paper proposes a technique for reducing energy consumed by hybrid caches that have both SRAM and STT-RAM (Spin-Transfer Torque RAM) in multi-core architecture. It is based on dynamic partitioning of the SRAM cache as well as the STT-RAM cache. It assigns cache blocks to a specific region of a cache based on an existing technique called read-write aware region-based hybrid cache architecture. Thus, when a store operation from a core causes a write miss, the block is assigned to the SRAM cache. When a load operation from a core causes a read miss and thus causes a block fill, the block is assigned to the STT-RAM cache. However, if the core is already using maximum cache ways allocated to it in the SRAM, then the block fill is done into the SRAM. The partitioning is updated periodically. Simulation results show that the proposed technique improves the performance of the multi-core architecture and significantly reduces energy consumption in the hybrid caches compared to the state-of-the-art migration-based hybrid cache management.