Decimal engine for energy-efficient multicore processors

Prior work demonstrated the use of specialized pro-cessors, or accelerators, be energy-efficient for binary floating-point (BFP) division and square root, and for decimal floating-point (DFP) operations. In the dark silicon era, where not all the circuits on the die can be powered simultaneously, we propose a hybrid BFP/DFP engine to perform BFP division and DFP addition, multiplication and division. The main purpose of this engine is to offload the binary floating-point units for this type of operations and reduce the latency for decimal operations, and power and temperature for the whole die.