DocumentCode
1791504
Title
Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip
Author
Manna, Kanchan ; Chattopadhyay, Subrata ; Sengupta, Indranil
Author_Institution
Sch. of Inf. Technol., Indian Inst. of Technol. Kharagpur, Kharagpur, India
fYear
2014
fDate
6-8 Oct. 2014
Firstpage
1
Lastpage
6
Abstract
This paper presents a combined solution to the Through-Silicon-Via (TSV) placement and mapping of cores to routers in a three-dimensional Network-on-Chip (NoC) design. It takes care of TSV geometries and communication requirements between cores. Comparison has been carried out with the recent 3D mapping results. Both static and dynamic performance have been considered. It shows that an intelligent placement of TSVs coupled with mapping can improve the performance significantly.
Keywords
integrated circuit design; network-on-chip; three-dimensional integrated circuits; 3D mapping; 3D mesh based network-on-chip; NoC design; TSV geometry; three-dimensional network-on-chip design; through silicon via mapping strategy; through silicon via placement strategy; Bandwidth; Benchmark testing; Network-on-chip; Routing; Three-dimensional displays; Through-silicon vias; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on
Conference_Location
Playa del Carmen
Type
conf
DOI
10.1109/VLSI-SoC.2014.7004177
Filename
7004177
Link To Document