Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation

Due to the time to market (TTM) pressures for System on Chip (SoC), improvements in validation methodology are needed to reduce the time to launch products. Current high speed links run hundreds of signals at Gigabit per second data rates over one or two connectors and tens of inches of backplane. Suitable connectors have to fulfill tight crosstalk, reflection, and attenuation specifications. Accurate connector measurements and models are critical to the successful design of the whole link. However, due to high pin count and interdependencies with the backplane environment connector characterization is still a challenging task. In this paper a new enhanced electrical validation testing methodology is presented, focusing on Ethernet post silicon validation over backplane. This paper shows that it is possible to obtain similar results (voltage and timing) using a frequency dependent attenuator (FDA) as using commercial backplane. The results were obtained at 2.5Gbps.