Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump

This paper presents the design of a sampling switch to be used in the input interface to an ultra low-power 8-bit, 1-kS/s SAR ADC in 65 nm CMOS working at a supply voltage of 0.4 V. Important design trade-offs for the sampling switch in this low-voltage and low-power scenario are elaborated upon. The design of a multi-stage charge pump which generates the requisite boosted control voltage is described. A combination of the multi-stage charge pump and a leakage-reduced transmission-gate (TG) switch meets the speed requirement while mitigating leakage without employing additional voltages. Performance of the sampling switch has been characterized over process and temperature (PT) corners. In post-layout simulation, the sampling switch provides a linearity corresponding to 9.42 bits to 13.5 bits over PT corners with a worst-case power consumption of 216 pW while occupying an area of 25.4 μm × 24.7 μm.