A 10 bit 16 MS/s redundant SAR ADC with flexible window function for a digitally controlled DC-DC converter in 28 nm CMOS

A 10 bit charge redistribution SAR ADC for digitally controlled DC-DC converters is presented. A redundant search is applied to increase the conversion rate. The required digital circuitry for calculation of the redundant search tree allows implementation of a window mode, where only a reduced input range is converted. The window function enables further speed enhancement without an increase of clock frequency and power consumption. Fabricated in 28 nm SLP CMOS the ADC occupies only 110×85 μm². In full range mode a conversion rate of 16 MS/s is achieved and in window mode 26.7 MS/s, respectively. With a measured total power consumption of 710 μ\\ν and 9.1 bit ENOB a FOM of 81 f J/conv-step is reached. A large input range with constant resolution, highly linear characteristic, and high robustness to PVT variations makes this ADC superior to delay line or ring oscillator based window ADCs.