Design considerations for interface circuits to low-voltage piezoelectric energy harvesters

In this work we investigate the limitations and describe the operation of passive fully integrated rectifiers in standard CMOS technology for low-voltage piezoelectric harvesters. These harvesters are typical for low-frequency and low-acceleration applications, such as body-motion scenarios, i.e., wearables. We motivate the choice of active rectifiers for low-voltage energy harvesters and techniques to boost the available input voltage to the rectifier. A test circuit recently taped-out in 0.35-μm CMOS is described to illustrate some of the challenges associated with rectifier design for low-voltage energy harvesters. The circuit occupies an area of 210 × 155 μm² and operates at input voltages between 0.6 and 3.3 V. Post-layout simulations shows an efficiency of 79 % at a 0.7-V input.