Design of low phase noise K-band Voltage-Controlled Oscillator using 180 nm CMOS and integrated passive device technologies

This paper presents a low power and low phase noise K-band VCO using 180 nm CMOS and integrated passive device (IPD) technologies. The cross-coupling circuit in this design is composed of P-type MOSs instead of N-type. Employing PMOS results in lower flicker noise but reduces the negative transconductance (-g_m). Since the IPD inductor has low parasitic resistance, the -g_m generated using PMOSs can fulfill the oscillation condition for the A>band VCO. Moreover, the high-Q IPD inductor is beneficial to phase noise. The flip-chip technique is applied to assemble the CMOS and IPD structures. The oscillation frequency is from 22.6 GHz to 24.5 GHz and the minimum phase noise is -111.4 dBc/Hz at 1 MHz offset. The DC power consumption is as low as 3.4 mW from a supply voltage of 1V.